High performance scalable elliptic curve cryptosystem processor for Koblitz curves

A scalable elliptic curve cryptography (ECC) processor is presented in this paper. The proposed ECC processor supports all five Koblitz curves recommended by the National Institute of Standards and Technology (NIST) without the need to reconfigure the FPGA. The paper proposes a finite field arithmetic unit (FFAU) that reduces the number of clock cycles required to compute the elliptic curve point multiplication (ECPM) operation for ECC. The paper also presents an improved point addition (PADD) algorithm to take advantage of the novel FFAU architecture. A scalable ECC processor (ECP) that is completely implemented in hardware that makes use of the novel PADD algorithm and FFAU is also presented in this paper.The design is synthesized and implemented for a target Virtex-4 XC4VFX12 FPGA. It uses 2431 slices, 1219 slice registers, 3815 four-input look-up tables (LUT) and can run at a maximum frequency of 155.376 MHz. The proposed design is the fastest scalable ECP that supports all five Koblitz curves known to the authors as it evaluates the ECPM for K-163 in 0.273 ms, K-233 in 0.604 ms, K-283 in 0.735 ms, K-409 in 1.926 ms and K-571 in 4.335 ms. The proposed design is suitable for server-side security applications where both high-speed and scalability are important design factors.