Multi bit random and burst error correction code with crosstalk avoidance for reliable on chip interconnection links

We propose an energy efficient error control code for the on chip interconnection link capable of correcting any type of error patterns including random and burst errors up to five (i.e. 1, 2, 3, 4, and 5 errors). The proposed code is based on single error correction–double error detection (SEC–DED) extended Hamming code and standard triplication error correction scheme. Using single error correction–double error detection (SEC–DED) extended Hamming code and standard triplication error correction scheme a new decoding algorithm is proposed to correct multiple errors up to five in on-chip interconnection link. Triplication error correction scheme provides crosstalk avoidance by reducing the coupling capacitance of the interconnection wire. The proposed code provides high reliability compared to other error control codes. The performance of the proposed code is evaluated for codec area, codec power, codec delay, residual flit error rate, link swing voltage and link power. For the given reliability requirement of 10−5 and 10−20, the proposed code achieves low residual flit error rate and low swing voltage. The low swing voltage results in the reduction of the link power consumption up to 68% compared to the existing error control codes for on chip interconnection link. The low residual flit error rate and low link power make the proposed code appropriate for on chip interconnection link.