Dynamically reconfigurable entropy coder for multi-standard video adaptation using FaRM

Dynamic and Partial Reconfiguration (DPR) is a feature present in modern Xilinx FPGAs, bringing flexibility to a whole new level. However, it is not yet wide spread in the industry because of poor performance and a lack of a cost model to estimate a solution early in the design process. In this paper, we present our methodology for developing systems capable of dynamic and partial reconfiguration with strict real-time constraints. Our approach is based on FaRM (Fast Reconfiguration Manager), a high-speed controller reaching the configuration port theoretical throughput in Xilinx FPGAs. FaRM performance is estimated using a cost model, which allows us to determine the optimum FIFO size to satisfy timing constraints with the best resources trade-off. We validate our approach with a video application that should be able to encode an H.264 (HD) and an MPEG-2 (SD) stream at the same time. For this we used two entropy encoders on the same reconfigurable zone, while satisfying constraints determined by the video streams. This is the first step of a fully reconfigurable video adaptation system. We also present our unified reconfigurable zone interfaces, specific to video adaptation.