VLSI architecture for parallel radix-4 CORDIC

COordinate Rotation DIgital Computer (CORDIC) algorithm is an iterative method for fast hardware implementation of the elementary functions such as trigonometric, inverse trigonometric, logarithm, exponential, multiplication and division functions in a simple and elegant way. This paper presents a regular and scalable VLSI architecture for the implementation of parallel radix-4 rotational CORDIC algorithm. Thorough comparison of the proposed architecture with the available architectures has been carried out to show the latency and the hardware improvement. Furthermore, the proposed architecture is coded for 16-bit precision using the VHDL language. The functionally simulated net list has been synthesized with 90 nm CMOS technology library and the area-time measures are provided. This architecture is also implemented using Xilinx ISE7.1i software and a Virtex device.