Reconfigurable system for high-speed and diversified AES using FPGA

In this article, we present a FPGA-based reconfigurable system for the advanced encryption standard (AES) algorithm. This proposed design, called diversified AES (DAES), has the variations of four parameters: the field irreducible polynomial, the affine transformation in the SubBytes, the offsets in the ShiftRows, and the polynomial in the MixColumns. The advantage of such variations in the AES system is that they increase the strength regarding internal or external attacks. We also use straightforward architecture – look-up tables – for encryption and decryption to lead this system simple and high-speed using field programmable gate arrays (FPGAs).