A compact hardware architecture for digital image stabilization using integral projections

• We present a hardware architecture for real-time digital video stabilization.
• The results are comparable to a full cross-correlation-based estimator.
• The architecture is tailored for compact and high-performance embedded systems.
• We designed and implemented a prototype on a field-programmable gate array (FPGA).
• The stabilization core uses 24.16 mW of power and less than 3.5% of FPGA resources.

We present a hardware architecture for real-time digital video stabilization for high-performance embedded systems. The stabilization algorithm analyzes the current and past video frames and obtains a motion estimation vector, which is then filtered to isolate unwanted camera movements from intentional panning. The vector is then used to correct the output video frame. The paper describes our hardware architecture for motion estimation, filtering and correction and its implementation on a Xilinx Spartan-6 LX45 FPGA. We evaluate our results on several benchmark video sequences, both visually and using the Inter-frame Transformation Fidelity index (ITF). Running on the 640×480640×480-pixel video output of an infrared camera, our FPGA implementation successfully compensates involuntary camera motion at a maximum throughput of 104.15 frames per second with a 100 MHz clock. The power consumption added to the FPGA by the image stabilization core is only 24.16 mW.