Hardware resource utilization optimization in FPGA-based Heterogeneous MPSoC architectures

Next generation FPGA circuits will allow the integration of dozens of hard and soft cores as well as dedicated accelerators in the same chip. These Heterogeneous Multiprocessor System-on-Chip (Ht-MPSoC) architectures will allow the design of very complex System-on-Chips (SoC) on a single FPGA chip and will fulfill modern application requirements, in terms of performance/energy consumption ratio. In this paper, we extend existing FPGA-based Ht-MPSoC architectures by considering sharing hardware accelerators among the cores. In these architectures, cores on the FPGA may have different resources that can be shared in different manners. To explore the large space of possible configurations of Ht-MPSoC on FPGA, designer needs a fast and accurate exploration tool. For this reason, a Mixed Integer Programming (MIP) model is also proposed to determine the Ht-MPSoC configuration that consumes the least HW resources while respecting the application execution time constraints. Using our MIP model, the design space of several hundreds of private and shared HW accelerators can be explored in a reasonable time with high accuracy.