A low cost architecture for high performance face detection

• The architecture has six individual dual-port SRAMs for flexible data access.
• The integral image is kept in registers and can be calculated in one clock cycle.
• The square values are calculated by a ROM and few simple shift operations.
• 4-stage pipeline architecture according to feature calculation feature.

Face detection has been playing an important role in numerous fields in recent years, and is considered to be a promising technology in the future. However, low cost implementation is still a difficulty due to huge computation of detection algorithm, especially when the detection is required to be applied in embedded systems. In this paper, a new architecture is proposed based on an efficient face detection algorithm. The architecture has three contributions. The first is a specially designed frame buffer which improves the data access efficiency and provides a big data throughput. The second is a new integral image refresh method, which can renew the integral image in one clock cycle to provide feature values for classification timely. The third contribution is a 4-stage pipeline structure for feature calculation, which improves the classification speed by 3 times almost without any increase in hardware area. The experiment results show that the architecture consumes less hardware and power resources while retaining a high-level of detection capability in processing 1024 × 1024 images.