CRANarch: A feasible processor micro-architecture for Cloud Radio Access Network

Cloud Radio Access Network (C-RAN) becomes a promising infrastructure, which can improve hardware resource utilization of traditional Radio Access Network (RAN). For C-RAN, data centers are essential hardware platform, and these data centers are universally equipped with general commercial multi-core processors which are not designed for wireless communication protocols dedicatedly. In this paper, firstly, we evaluate performance bottlenecks of general multi-core processors with current dominant micro-architecture via typical wireless communication protocol. The results show that the dominant micro-architecture mismatches to demands of wireless communication protocols, which makes dominant general multi-core processor is inefficient when used in this application field. Secondly, we analyze the essential micro-architectural level reasons for the inefficiency in detail. A typical characteristic of wireless communication protocols is there are lots of random memory accesses in a large memory address space, which results in high miss ratio of on-chip cache hierarchies. The frequent on-chip cache misses result in amounts of off-chip memory access operations, which incurs longer memory access latency as a dominant factor to degrade overall performance. Based on the results, we identify key micro-architectural characteristics that meet demands of wireless communication protocols. Finally, we propose a feasible micro-architecture of multi-core processor for C-RAN, called as CRANarch, the performance results show its improved hardware utilization efficiency and power efficiency when used in C-RAN data centers.