An embedded processor core for consumer appliances with 5.6 GFLOPS and 73M polygons/s FPU

A SuperH™ embedded processor core, SH-X2, implemented in a 90-nm CMOS process running at 800 MHz achieved 1440 Dhrystone MIPS, 5.6 GFLOPS, and 73M polygons/s. It has a dual-issue eight-stage pipeline architecture, but maintains the 1.8 MIPS/MHz of the previous seven-stage processor core SH-X. The processor meets the requirements of a wide range of applications, and is suitable for digital appliances aimed at the consumer market, such as cellular phones, digital still/video cameras, and car navigation systems. This paper focuses on the implementation of floating-point units in the SH-X2 and its resulting performance, and considers ways of enhancing this performance in future.