Soft-decision forward error correction for 100 Gb/s digital coherent systems

Soft-decision forward error correction (SD-FEC) and its practical implementation for 100 Gb/s digital coherent systems are discussed. In applying SD-FEC to a digital coherent transponder, the configuration of the frame structure of the FEC becomes a key issue. We present a triple-concatenated FEC, with a pair of concatenated hard-decision FEC (HD-FEC) further concatenated with an SD-based low-density parity-check (LDPC) code for 20.5% redundancy. In order to evaluate error correcting performance of SD-based LDPC code. We implement the entire 100 Gb/s throughput of LDPC code on field programmable gate arrays (FPGAs) based hardware emulator. The proposed triple-concatenated FEC can achieve a Q-limit of 6.4 dB and a net coding gain (NCG) of 10.8 dB at a post-FEC bit error ratio (BER) of 10−15 is expected. In addition, we raise an important question for the definition of NCG in digital coherent systems with and without differential quadrature phase-shift keying (QPSK) coding, which is generally used to avoid phase slip caused by the practical limitations in processing the phase recovery algorithms.

► Soft-decision forward error correction for 100 Gb/s digital coherent systems is discussed.
► We propose a triple-concatenated FEC for 20.5% redundancy.
► We implement the entire 100 Gb/s throughput of LDPC code on a hardware emulator.
► The soft-decision FEC can achieve a net coding gain of 10.8 dB at a BER of 10−15.