A new IDDT test approach and its efficiency in covering resistive opens in SRAM arrays

• Novel dynamic supply current approaches are presented in order to unveil resistive open defects.
• The probability of open defect distribution in SRAMs was estimated.
• The efficiency of presented approaches in covering open defects is verified on a 4096-bit SRAM array.
• The effect of the leakage current on the power supply voltage, and efficiency is investigated.

In this article, an alternative approach to SRAM testing – the dynamic supply current test is presented, which is used to cover resistive opens considered as “hard detectable” type of physical defects. The investigation of the efficiency in unveiling open defects is based on the evaluation analysis carried out on a six transistor (6T) SRAM cell designed in a 90 nm CMOS technology, where parasitic components of word lines, bit lines, and power supply lines are derived from a 4096-bit SRAM array. Three possible approaches to the dynamic supply current test are proposed and compared. Finally, achieved results are analyzed and discussed.