A high performance ST-Box based unified AES encryption/decryption architecture on FPGA

• A single integrated and symmetric ST-Box structure followed by a single XOR Network is proposed for a unified AES encryptor and decryptor architecture.
• Switching capabilities of BRAM are explored to maximize the performance of system by proposing a duty-cycle based accessing technique.
• The Effectiveness of unified AES encryptor and decryptor core is then evaluated in both iterative and pipelined architectures.
• Our single-unit AES encryptor and decryptor cores on Virtex-7 FPGA result in highest design efficiencies.

In this paper, a unified Field Programmable Gate Array (FPGA) based Advanced Encryption Standard (AES) encryptor/decryptor design is presented by proposing a symmetric ST-Box structure. This structure fully utilizes high capacity (32 Kb) Block RAM (BRAM) by accommodating all encryption and decryption lookup operations within a single BRAM in the form of single integrated Look-Up-Table. This design also caters the inherent asymmetric nature of encryption and decryption coefficients for a unified hardware. Further the symmetry at BRAM output is maintained to use a single XOR network during both encryption and decryption. The performance of design is enhanced by proposing a duty-cycle based accessing technique. It explores the switching capabilities of BRAM and effectively minimizes the ON time of BRAM by changing duty-cycle of input clock. This enables us to access single BRAM 4 times per clock. Effectiveness of design is further measured by implementing it, in both iterative and pipelined architectures. Our proposed iterative design on Virtex-7 proved to be the smallest 128-bit unified AES core with 48.70% reduced resources and the best Throughput Per Slice (TPS) of 11.56. Similarly our pipelined design saved 59.01% area and has the highest throughput of 45.69 Gbps.