A high speed, memory efficient line based VLSI architecture for the dual mode inverse discrete wavelet transform of JPEG2000 decoder

In this paper, a high speed, memory efficient VLSI architecture has been presented for dual mode (9/7 lossy and 5/3 lossless filters) line based inverse discrete wavelet transform (IDWT) to support JPEG 2000 decoder. The new algorithm has been developed to reduce the critical path and on chip memory requirements in the proposed design. Multipliers are implemented with shift and add technique to reduce the critical path to an adder delay (Ta) and achieve maximum possible frequency for both modes. The on chip memory requirement of the M × N 2-D lossy and lossless IDWT filters are 5N and 3N, respectively. The comparison of results shows that the proposed design surpasses previous line based IDWT architectures in the aspects of less on chip memory requirements and shortest critical path delay. This architecture supports line based approach, where the input images are scanned line by line and, both vertical and horizontal filtering operations execute simultaneously to reconstruct the images. The proposed architecture is synthesized and implemented in Xilinx xc4vfx100-12 device and is offering the maximum frequency of 306 MHz for an 512 × 512 image. Power analysis performed using Synopsys Design Compiler with UMC 90-nm CMOS process, it consumes 130 mW power at 306 MHz frequency. The implementation results show that the proposed architecture can support even digital cinema (image resolution: 4096 × 1080) with 3 levels recomposition at 90 frames/s.