کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
462646 696882 2015 14 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Design and implementation of novel, fast, pipelined HSI2RGB and log-hybrid RGB2HSI colour converter architectures for image enhancement
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر شبکه های کامپیوتری و ارتباطات
پیش نمایش صفحه اول مقاله
Design and implementation of novel, fast, pipelined HSI2RGB and log-hybrid RGB2HSI colour converter architectures for image enhancement
چکیده انگلیسی


• Developed a novel, low complexity, high speed hardware solution for RGB2HSI and HSI to RGB conversion.
• Implemented HSI hardware architecture reduces demands on hardware multiplier resources and eliminates division using fast bit shifting.
• Implemented architecture yields better colour rendition using HSI colour space compared with RGB colour enhancement.
• Developed modular RGB2HSI and HSI2RGB converter architectures for colour image enhancement and segmentation hardware systems.
• Implemented an improved image colour and contrast enhancement algorithm hardware architecture utilizing the fast HSI converter.

This paper presents a novel, modular, high speed, original FPGA hardware architecture implementation for HSI2RGB conversion in addition to a novel, multiplierless, log-based, modular RGB2HSI colour space converter architecture and its improved, faster, pipelined version. Contributions of the paper include the use of relatively minimized interpolated LUTs to approximate trigonometric quotient relationships with miniscule ranges, the elimination of costly variable divisions in the hardware architectures of the RGB2HSI and HSI2RGB converters, the conversion of crucial, unavoidable variable divisions to fast bit shifting operations, while maintaining a reasonable level of accuracy in the HSI2RGB computation, ultimately, creating a complete, modular, high performance HSI converter hardware architecture that can easily be incorporated into existing or new log-based image enhancement architectures for processing low contrast, dark images with uneven illumination to improve colour rendition. The architecture was designed for a Virtex 5 FPGA (xc5vlx50t-1fft1136) for real-time use and implementation and simulation results indicate that the proposed system yields images with improved colour rendition when compared to image enhancement algorithms such as Homomorphic filtering and Multiscale Scale Retinex (MSR).

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microprocessors and Microsystems - Volume 39, Issues 4–5, June–July 2015, Pages 223–236
نویسندگان
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