SAT-based generation of compressed skewed-load tests for transition delay faults

Skewed-load tests ensure application of delay tests to logic cores of system-on-chip with only one storage element per cell in the wrapper boundary register and in the internal scan chain. This resolves the test area problem but the fault coverage and the test application time still require optimization efforts. The satisfiability-based test pattern generator of compressed skewed-load tests for transition delay fault is proposed. It represents a new efficient approach for generating compressed skewed-load tests because the test is gradually generated without the need of a pre-generated set of initialization and excitation vectors. Two optimization methods are also proposed. The first method, the wrapper cell ordering method, increases the fault coverage by reducing the shift dependence of skewed-load tests. The second method, the fault ordering method, ensures shorter tests by determining the order in which the faults will be targeted during the test generation and consequently, the new test vectors can overlap the test sequence in the greatest degree. The proposed methods were evaluated over benchmark circuits and the experimental results show higher fault coverages and shorter test lengths.