Energy optimization of Application-Specific Instruction-Set Processors by using hardware accelerators in semicustom ICs technology

The increasing complexity of applications with a decreasing time-to-market requirement has created a strong interest in both high-performance and flexible embedded processors with a strong consideration for battery life. Low-power optimizations are therefore often applied toward the development of Application-Specific Instruction-Set Processors (ASIPs). In this paper ASIP accelerators for a typical DSP task are developed and synthesis results from six different cell-based and FPGA architectures are shown.By carefully analyzing algorithms and implementing appropriate accelerators with logic, it is shown that an increase in design performance is achieved while still reducing energy consumption due to the reduced latency of the task. In addition, we show cases when classic synthesis options can outperform new power optimization features in Xilinx ISE 11.1.

► We examine design issues of tight couple hardware accelerators in Application-Specific Instruction-Set Processors.
► A true vector processor design is developed using the architecture description language LISA.
► Embedded microprocessor design flow to achieve minimum energy consumption is presented.
► FPGA synthesis options for low energy microprocessor designs are compared.
► Cell-based ASIC synthesis results with the goal of minimum energy consumption for DSP task are shown.