A hyperscalar dual-core architecture for embedded systems

This paper proposes a lightweight reconfigurable dual-core architecture for embedded systems, called hyperscalar dual-core architecture. The proposed architecture can play three different roles (a 2-issue statically scheduled superscalar processor, a homogeneous dual-core processor, or a standalone single-core processor), allowing embedded systems to accommodate diverse workloads. The proposed design uses four extended instructions to enable programmers to dynamically switch the roles of the proposed architecture. This paper also presents an instruction analyzer (IA) that connects two scalar in-order cores to handle role switching. The design of IA makes it possible for the two cores to work together like a 2-issue statically scheduled superscalar processor. Based on the proposed dispatching rules, the IA dispatches instructions with data dependencies to the same core. Since two cores act like a statically scheduled superscalar processor, they can resolve data dependencies using existing forwarding paths without introducing the high-area-cost inter-core operand-switching crossbars. Simulation results show that when the proposed architecture works in a statically scheduled superscalar manner, it achieves a 26% higher instructions per cycle (IPC) averaged across all 29 benchmarks from the MiBench suite than a scalar in-order core. The increases in area and power to extend a homogeneous dual-core processor to a hyperscalar dual-core processor are only 1.8% and 1.75%, respectively, using 90 nm CMOS technology.