Parameterized MAC unit generation for a scalable embedded DSP core

This paper describes the architecture and hardware generation concept of a parameterized MAC unit for use in a scalable embedded DSP core. The MAC unit supports a broad set of instructions for integer and fractional datatypes. Its generation is controlled by architectural as well as implementation and placement parameters. Including structured physical placement in the generation process ensures fast and predictable performance estimation. Especially for modern technologies, where wire effects dominate the achievable performance of a circuit, tight control of cell placement makes a predictable quantitative analysis and optimization possible.In the context of early-stage design space exploration, which is used to determine an optimal DSP core architecture, the presented methodology allows a fast and consistent estimation of the MAC unit’s performance characteristics for various “what if” scenarios. Also implementation bottlenecks can be identified in an early project phase. In the context of the subsequent implementation phase, it enables local, detailed, and predictable quantitative design optimizations.