کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
462920 | 696930 | 2010 | 10 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
High speed c-means clustering in reconfigurable hardware
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
شبکه های کامپیوتری و ارتباطات
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چکیده انگلیسی
A novel hardware architecture for c-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. A simple divider circuit based on lookup table, multiplication and shift operations is employed for reducing both the area cost and latency for centroid computation. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on an FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for c-means design.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microprocessors and Microsystems - Volume 34, Issue 6, October 2010, Pages 237-246
Journal: Microprocessors and Microsystems - Volume 34, Issue 6, October 2010, Pages 237-246
نویسندگان
Wen-Jyi Hwang, Chih-Chieh Hsu, Hui-Ya Li, Sheng-Kai Weng, Tsung-Yi Yu,