Partial access conflict-relieving programmable address shuffler for parallel memory system in multi-core processor

The advancement of process technology enables the integration of multiple cores featuring parallel processing of several tasks in a single die. The requirement of extensive memory bandwidth puts a major performance bottleneck in the multi-core architecture for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions required by multiple cores, memory access conflicts caused by simultaneous accesses to an identical memory page by two or several cores limit the performance of the multi-core architecture. We propose and evaluate the programmable memory address shuffler associated with the novel memory shuffling algorithm integrated in multi-core architecture with parallel memory system. The address shuffler efficiently translates the requested memory addresses into the shuffled addresses such that the amount of simultaneous accesses to an identical physical memory diminishes. Programmability of the address shuffler enables the adaptive address shuffling depending on application-specific memory access patterns. The proposed shuffling algorithm relocates partitioned memory sub-pages based on memory access conflict graph obtained by profiling memory access pattern of an application. We demonstrate that the shuffled sub-pages are represented by cyclic linked list which enables partial address shuffling with the minimal number of shuffling table entries reducing hardware complexity. The programmable address shuffler reduces the amount of access conflicts by 83% for pitch-shifting audio decompression.