Design of an efficient dual mode reconfigurable FIR filter architecture in speech signal processing

Modern Digital Signal Processing systems require the reconfigurable FIR filters with low complexity architectures. This paper presents a novel architecture for low power and low area implementation of reconfigurable Finite Impulse Response (FIR) filter based on dual mode operation. The proposed reconfigurable technique operates in two modes. One mode is a multiplier less implementation in which area complexity is reduced and another mode is a testable reversible mode of operation to achieve low power. Cadence Encounter synthesis results of the designed 75 taps filter architecture achieve power savings up to 37.97% and area reduction of about 44.61% over the conventional reconfigurable architectures. The performance metric MSE, PSNR and SMR values of proposed dual mode reconfigurable 75 taps FIR filters are found to be 0.62, 50.24 and 80.8506 respectively.