کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
462991 | 696939 | 2015 | 12 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
P2IP: A novel low-latency Programmable Pipeline Image Processor
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
شبکه های کامپیوتری و ارتباطات
پیش نمایش صفحه اول مقاله
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چکیده انگلیسی
This paper presents a novel systolic Coarse-Grained Reconfigurable Architecture for real-time image and video processing called P2IP. The P2IP is a scalable architecture that combines the low-latency characteristic of systolic array architectures with a runtime reconfigurable datapath. Reconfigurability of the P2IP enables it to perform a wide range of image pre-processing tasks directly on a pixel stream. The versatility of the P2IP is demonstrated through three image processing algorithms mapped onto the architecture, implemented in an FPGA-based platform. The obtained results show that the P2IP can achieve up to 129 fps in Full HD 1080p and 32 fps in 4K 2160p what makes it suitable for modern high-definition applications.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microprocessors and Microsystems - Volume 39, Issue 7, October 2015, Pages 529–540
Journal: Microprocessors and Microsystems - Volume 39, Issue 7, October 2015, Pages 529–540
نویسندگان
Paulo Possa, Naim Harb, Eva Dokládalová, Carlos Valderrama,