Performance effects of pipeline architecture on an FPGA-based binary32 floating point multiplier

High pipeline depth architecture with pipeline stage more than five is rarely adopted in existing multipliers for real world applications. In this paper, a field programmable gate array (FPGA) based binary32 floating point multiplier (FPM) is presented to support variety of pipeline depth and the effects of pipeline architecture have been investigated. Pipeline architecture is formulated based on radix-4 Booth recoding approach, an improved Wallace tree, and partial product accumulation. Upon detail and quantitative investigation on the proposed architecture on both cutting edge Xilinx and Altera devices, pipeline depth affects maximum running frequency much more than power consumption, and the pipeline depth should be limited to obtain maximum running frequency for binary32 FPM on both cutting edge target devices, which is consistent to the previous study. Meanwhile, the study demonstrates the pipeline depth to reach at peak performance is lower than that of targeting at FPGA device with 4-input LUTs years ago.