FPGA for pseudorandom generator cryptanalysis

FPGAs have been successfully applied for cryptanalytic purposes, particularly in exhaustive key search that is a highly parallelizable task. In this work, we consider a pseudorandom generator scheme that consists of a number of subgenerators, the first of which is a linear feedback shift register (LFSR). LFSR is often used in cipher systems because of good cryptographic characteristics of its output sequence. The cryptanalysis has shown that if noisy prefix of the output sequence of this generator is known, it is possible to reconstruct the initial state of the LFSR by means of generalized correlated attack. The attack is based on the resolving of the constrained edit distance between the sequences determined by the initial states of the shift registers and the intercepted noisy output sequence. The systolic array architecture exploits the intrinsic parallelism of the dynamic programming algorithm for edit distance computation and achieve reductions in computation time of several orders of magnitude comparing with sequential calculation that is characteristic for software solutions. With a minimum increase of area, our design doubles the speed of similar approaches that are applied in bioinformatics, since there are no published ones for cryptanalysis. The obtained results on Xilinx Virtex and Virtex2 FPGA families also holds when a bus is connected, since our design takes into account the bus I/O bottleneck (i.e. PCI).