Real-time disparity map computation module

Stereo vision deals with images acquired by a stereo camera setup, where the disparity between the stereo images allows depth estimation within a scene. 3D information, hence, is retrieved which is essential in many machine vision applications. Disparity map extraction of an image is a computationally demanding task. Previous work on disparity map computation is mainly limited to software based techniques on general-purpose architectures. In this paper a new hardware-efficient real-time disparity map computation module is developed. This enables a hardware-based cellular automata (CA) parallel-pipelined design, for the overall module, realized on a single FPGA device, the typical operating frequency of which is 256 MHz. Accurate disparity maps are computed at a rate of nearly 275 per second, for a stereo image pair with a disparity range of 80 pixels and 640 × 480 pixels spatial resolution. The presented hardware-based algorithm provides very good processing speed at the expense of accuracy, with very good scalability in terms of disparity levels. The proposed method allows the fastest disparity map computational module to be built, to the best of the authors’ knowledge so far, enabling a suitable module for real-time stereo vision applications.