GPGPU accelerated Krylov methods for compact modeling of on-chip passive integrated structures within the Chameleon-RF workflow

Continued device scaling into the nanometer region and high frequencies of operation well into the multi-GHz region has given rise to new effects that previously had negligible impact but now present greater challenges and unprecedented complexity to designing successful mixed-signal silicon. The Chameleon-RF project was conceived to address these challenges. Creative use of domain decomposition, multi grid techniques or reduced order modeling techniques (ROM) can be selectively applied at all levels of the process to efficiently prune down degrees of freedom (DoFs). However, the simulation of complex systems within a reasonable amount of time remains a computational challenge. This paper presents work done in the incorporation of GPGPU technology to accelerate Krylov based algorithms used for compact modeling of on-chip passive integrated structures within the workflow of the Chameleon-RF project. Based upon insight gained from work done above, a novel GPGPU accelerated algorithm was developed for the Krylov ROM (kROM) methods and is described here for the benefit of the wider community.