Area Efficient Complex Floating Point Multiplier for Reconfigurable FFT/IFFT Processor Based on Vedic Algorithm

The need of complex multipliers in mathematics seems to be a very important aspect. The application used as a complex operation with respect to the real and imaginary numbers together. In many of the practical aspect the design substantiated to be a aiding hand for co-functionality units. Since to carry out the operations more correctly so as to elluct the technical peccadilloes. The results show that proposed FFT consumes very less resources in terms of slices, flip flops and multipliers to provide cost effective solution for DSP applications The proposed design has a desideratum for high efficacy eliciting structure in terms of accuracy. The device used in this proposed design is 7a30tcsg324-3.