8-Bit 250-MS/s ADC Based on SAR Architecture with Novel Comparator at 70 nm Technology Node

The data converters are prerequisite for digital processing of analog signals. SAR ADC is preferred for their good balance between speed, area and power considerations. In this paper, we proposed a novel comparator design based on double tail architecture for an 8-bit successive approximation register analog-to-digital converter. We implemented 8 bit analog-to-digital converter contains a Successive Approximation register, Ring counter, SR-Latch, R2R Ladder type digital-to-analog convertor and a proposed novel comparator. The circuit is simulated using Predictive Technology model 70 nm Technology using Tanner EDA tool. The average INL and DNL are less than 1 LSB and 1 LSB, respectively. At the sample rate of 250 MHz (2 GHz clock Freq) and supply voltage of 1.2 V, the ADC consumed about 1.3 mW. The analog-to-digital converter using proposed comparator deign consumes less power and thus can be used in portable device.