Subthreshold Circuit Designing and Implementation of Finite Field Multiplier for Cryptography Application

Ultra-low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift where power dissipation has become as important consideration as performance and area. The sub-threshold region has made this logic an excellent choice, because power consumption is much lower due to the exponential decay of the active drain current.Along with low power consumption, security is another compelling requirement for some applications. Power analysis attack is a serious threat to devices with secret information inside. Under power analysis attack, attacker observes transmitted power of transmitter and can hack the secret information of the system. This paper presents the design and implementation of secure system under subthreshold condition, so that secure system is well cure from power analysis attack. Here in this paper we presented designing and implementation of finite field multiplier for cryptography applications.Finite field multiplier is the key component for implementing cryptographic operation. By developing standard subthreshold cell libraries of 6 elements, 4 bit digit-level finite field multiplier is implemented to operate in the subthreshold region. The power consumption of the subthreshold multiplier is 38nW, the speed of the multiplier is 250 KHz and energy per operation 0.6pJ at supply voltage 0.2 V is calculated. All circuits are simulated using Tanner EDA tool at 70 nm technology node.