Toward an FPGA Hardware Implementation of the Alamouti 4x2 Space-time Block Coding

In the recent years Space Time Block Coding has attracted the attention of the research community in the quest of optimizing the use of the bandwidth to support today's wireless communications applications. To achieve this aim, STBC exploits the spatial diversity. However, complexity challenges exacerbate when more than two transmit and more than one receive antennas are used. This paper presents the implementation of a low-complexity Maximum Likelihood (ML) decoding complexity of the Double Alamouti 4x2 STBC. The design exploits and takes advantage of the enhanced processing capability of an FPGA to achieve this aim. The scheme was first coded in MATLAB, then in ModelSim. Both MATLAB and VHDL performance results have been presented in terms of Symbol Error Rate (SER) versus Signal to Noise ratio (SNR) for 4-QAM.