VLSI Design and Implementation of Efficient Software Defined Radio Using Optimized Quadrature Direct Digital Frequency Synthesizer on FPGA

This paper presents an framework for efficient design and implementation of software defined radio (SDR) on FPGA platform using optimized Quadrature Direct Digital Frequency Synthesizer (QDDFS). An basic SDR System consists of RF Antennas, Analog to Digital converter (ADC), Digital to Analog converter (DAC), Filters and processing units. Reconfigurability and optimization can be achieved in the processing unit to a maximum extent. Processing unit of the SDR System is designed and implemented completely in this paper. The important parts of the SDR system designed are 16-Quadrature Amplitude Modulation (16-QAM), Orthogonal Frequency Division Multiplexing (OFDM) (16 point Fast Fourier Transforms (FFT), Inverse Fast Fourier Transform (IFFT) and Cyclic Prefix) and QDDFS. QDDFS generates the sine and cosine values in digital domain and it is optimized in terms of the device utilization with efficient performance and the functionality of rapidly hopping between the different frequencies, faster response time are also achieved. Both in transmitter and receiver, the same QDDFS architecture is used. The Input to the SDR system designed is Text Data which is fed and retrieved in the ASCII Format.