Power-aware Mapping for 3D-NoC Designs Using Genetic Algorithms

Scalable 3D Networks-on-Chip (NoC) designs are needed to match the ever-increasing communication and low-power demands of large-scale multi-core applications. However, chip designers do not have the necessary tools to implement their applications efficiently at different layers of the design hierarchy. A design methodology for low power 3D-NoCs applications is needed to achieve the best performance. To address this problem, we use Genetic Algorithms to find the best 3D-NoC mesh network mapping that achieves minimum power consumption for a given application. As a proof of concept, a case study of a multicore application that has 32 symmetric microprocessors is presented. We used Genetic Algorithms to calculate the fitness function and solve the optimization problem in less than four minutes, whereas it took over three days using exhaustive search and yet to find the minimum power consumption.