Abstractions for Executable and Checkable Fault Management Models

The work presented in this paper describes an approach used to develop SysML modeling patterns to express the logical behavior of fault protection (FP), test the model's logic via fault injection simulations, and verify the system's logical design via model checking. A FP model was architected with collaborating Statecharts that captures interactions between relevant system components (error monitors, FP engine, devices) and system behavior abstractions. Development of a method to implement verifiable and lightweight executable FP models enables future missions to have access to larger fault test domains and verifiable design patterns.