Reducing Delay and Quantum Cost in the Novel Design of Reversible Memory Elements

In a computational model, that uses transitions from one state of the abstract machine to another, a necessary condition for reversibility is that, the relation of the mapping from states to their successors must be one-to-one. In these works, the primary focus of design is to optimize number of reversible gates and garbage outputs. The calculation of number of gates is not a good option to check the complexity of a circuit as each gate has different architectural complexity decided by a parameter called quantum cost. Delay, hardly addressed in the existing works available in literature, is another good parameter to be optimized for fast reversible computation. In this work, we have presented novel designs of basic sequential circuits like latch that are optimum in terms of delay, quantum cost and garbage. We have also demonstrated quantum cost efficient D-FF, SR-FF, JK-FF & T-FF, along with their master slave configurations.