Exploiting Coarse-grained Parallelism in Multi-transform Architectures for H.264/AVC High Profile Codecs

A parallel Multi-Transform Architecture (MTA) for the computation of the 2-D transforms adopted in modern digital video stan- dards is proposed in this paper. This hardware structure can be dynamically configured to efficiently compute either one transform of size N × N, or k different transforms of size in simultaneous, where N ∈ N and k = 2i with i = 1, .., log2N − 1. The advantages offered by the proposed parallel architecture were assessed by implementing in a Xilinx Virtex-7 FPGA a proof-of-concept transform core compliant with the High Profiles of the H.264/AVC standard. The obtained results show that such processing structure is capable of achieving real-time operation for video sequences in the 8k Ultra High Definition Television (UHDTV) format (7680 × 4320 @ 30 fps). In addition, these results also demonstrate that the proposed parallel MTA allows to, at least, double both the throughput and the hardware efficiency of the implemented transform cores, when compared to the original design of thearchitecture.