An efficient approach to design a reversible control unit of a processor

Reversible logic has captured significant attention in recent time as reducing power consumption is one of the main concern of digital logic design. It consumes less power by recovering bit loss from its unique input–output mapping. In this paper, we propose a reversible control unit, which is first ever proposed in literature. Two new 4 × 4 reversible gates, namely HL gate and BJ gate, are proposed to design reversible decoder and J-K flip-flop. An algorithm has been shown to design a reversible control unit. On the way to design the control unit, we propose reversible decoder, sequence counter, instruction register and control logic gates. These circuits are analyzed with the existing ones. The comparative results show that the proposed design outperforms the existing designs in terms of numbers of gates, garbage outputs, delay and quantum cost. In addition, some lower bounds on the numbers of gates and garbage outputs of the proposed control unit have also been presented.