Design and implementation of low-power motion estimation based on modified full-search block motion estimation

Due to the increasing demand of data transfer in video process. Motion estimation is an important component in power-consumption of video codec. And the important thing to design the motion estimation is power optimization, which is achieved by carefully designing motion estimator. This paper is proposed with modified full-search block motion estimation algorithm for different video coding standard. The proposed architecture for full-search block motion estimation allows the frames into nine 16X16 sub-blocks. And finite-state machine is integrated with the proposed architecture for best block matching in the search area. In the proposed architecture, cells are used to store the current frame and compare the current frame with a reference frame to achieve the low-power by reusing the block. The proposed algorithm was designed using Verilog HDL and implemented in Altera FPGA using Altera Quartus II synthesis tool. Compare with the conventional architecture, our proposed architecture was designed with low power and area and high Peak signal to noise ratio (PSNR), which is 5 times faster than the conventional method.