A new intelligent hardware implementation based on field programmable gate array for chaotic systems

• This paper presents a new intelligent hardware implementation for chaotic systems.
• Intelligent hardware is based on the wavelet decomposition and neural network (NN).
• Wavelet decomposition was used for extracting feature and NN was used for modeling.
• Configurations have been simulated and tested under ModelSim Xilinx software.
• The best configuration has been implemented under the Xilinx Virtex-II Pro chip.

In the present study, a new intelligent hardware implementation was developed for chaotic systems by using field programmable gate array (FPGA). The success and superior properties of this new intelligent hardware implementation was shown by applying the Modified Van der Pol–Duffing Oscillator Circuit (MVPDOC). The validation of intelligent system model was tested with both software and hardware. For this purpose, initially the intelligent system model of MVPDOC was obtained by using the wavelet decompositions and Artificial Neural Network (ANN). Then, the intelligent system model obtained has been written in Very High Speed Integrated Circuit Hardware Description Language (VHDL). In the next step, these configurations have been simulated and tested under ModelSim Xilinx software. And finally the best configuration has been implemented under the Xilinx Virtex-II Pro FPGA (XC2V1000). Furthermore, the High Personal Simulation Program with Integrated Circuit Emphasis (HSPICE) simulation of MVPDOC has been carried out under ModelSim Xilinx software for comparison with proposed intelligent system. The results obtained show that the proposed intelligent system simulation has much higher speed in comparison with HSPICE simulation.

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