Pseudo differential multi-cell upset immune robust SRAM cell for ultra-low power applications

This paper presents a pseudo differential 12 transistor (PD12T) ultra-low leakage, fully half-select-free robust SRAM cell with good static and dynamic read/write performance. The proposed cell offers best Read/Hold SNM, Write Margin (WM) and least leakage power among all the cells considered in this work while causing an area overhead of 2.5× of that of 6T cell. Simulation results at VDD = 0.5 V show that PD12T cell offers 4.24× higher RSNM, 1.62× higher WM, 1.9× smaller leakage power (at 50 °C) as compared to 6T SRAM. The proposed cell offers VDD,min = 140 mV which is 260 mV smaller than that for 6T cell. When operated at VDD,min, the proposed cell consumes 13.6× smaller mean leakage power. The Ion/Ioff ratio of the proposed cell is more than 10× as compared to 6T cell and it holds potential to compensate for the area overhead by having more number of cells connected to the same bitline. The proposed cell is also suitable for all-TFET implementation as it requires only unidirectional current flow through transistors. Monte Carlo simulations using HSPICE with 16 nm PTM were performed by incorporating local and global variations and it is observed that the proposed cell offers high robustness against PVT variations. The proposed cell has highest critical charge among all other considered cells, which means that it is least vulnerable to soft-errors. The proposed PD12T also offers the best Electrical Quality Metric (EQM) among the cells considered in this work. The MC simulations for HSNM of row and column half-selected cells show that the mean value of SNM is approximately 30% of VDD. Therefore, the proposed cell can be used for bit-interleaving architecture to achieve multi-cell upset immunity and could be a good choice for applications that demands high stability, moderate speed and ultra-low power.