FPGA implementation of fractional-order chaotic systems

This paper presents the digital implementation of fractional-order (FO) chaotic systems on Field Programmable Gate Array (FPGA). In the proposed work Simulink model of each chaotic system is first realized using HDL coder of MATLAB, wherein each coefficient and signal is represented using a fixed number of bits. The construced design is translated into VHDL code using hardware generation block. This code is further translated into bitstream file using Quartus software. The chaotic system is implemented by downloading the obtained bitstream file into Altera FPGA Cyclone IV E (EP4CE11529C7N) chip. A methodology has been developed to construct FO chaotic system using HDL coder. Five different FO chaotic systems, viz., Lorenz, Chen, Lü, Arneodo, and Lorenz Hyperchaotic system have been presented in the paper to illustrate the methodology. The systems have been implemented on FPGA platform. Analysis of each chaotic system is carried out on the basis of hardware resource utilization, static power analysis and synthesis frequency on FPGA. The results show that FPGA provides high-speed realizations with the desired accuracy and low power consumption for FO chaotic systems.