An energy and area efficient yet high-speed square-root carry select adder structure

In this paper, we propose a modified carry select adder (CSLA) structure which is more power/energy and area-efficient compared to the existing CSLAs. The higher efficiency is achieved by modifying the logic formulations of the carry generation and selection (CGS) scheme and merging all of its redundant logic operations in the carry generation (CG) and carry selection (CS) units of the CGS-based CSLA (CGS-CSLA) structure. This leads to a simplified structure. Next, the proposed CSLA structure is employed to design efficient square-root CSLA (SQRT-CSLA) structure. The efficiency of the proposed SQRT-CSLA is investigated by comparing its speed, power, energy, and area parameters with those of some other SQRT-CSLA structures, including conventional SQRT-CSLA, binary to excess-1 converter, common Boolean logic, and the CGS-based SQRT-CSLA structures. The investigation, which is performed using HSPICE simulations based on a 45 nm bulk CMOS technology, includes 8, 16, 32, and 64-bit adder structures. The impact of voltage scaling on the efficiency of the proposed structure is also studied by changing the supply voltage levels from the near-threshold voltage to the nominal supply voltage. Simulation results reveal that the proposed SQRT-CSLA provides, at least, 14%, 14%, and 15% lower energy, energy-delay product, and area-delay product, respectively, compared to those of the CGS-based SQRT-CSLA structure, averaged over the supply voltage and bit length.