کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
4956670 | 1444589 | 2017 | 10 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Ascon hardware implementations and side-channel evaluation
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
شبکه های کامپیوتری و ارتباطات
پیش نمایش صفحه اول مقاله
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چکیده انگلیسی
Having ciphers that provide confidentiality and authenticity, that are fast in software and efficient in hardware, these are the goals of CAESAR, the Competition for Authenticated Encryption: Security, Applicability, and Robustness. In this paper, the CAESAR candidate Ascon is implemented in hardware and optimized for different typical applications to fully explore Ascon's design space. Thus, we are able to present hardware implementations of Ascon suitable for RFID tags, Wireless Sensor Nodes, Embedded Systems, and applications that need maximum performance. For instance, we show that an Ascon implementation with a single unrolled round transformation is only 7Â kGE large, but can process up to 5.5Gbit/sec of data (0.75 cycles/byte), which is already enough to encrypt a Gigabit Ethernet connection. Besides, Ascon is not only fast and small, it can also be easily protected against DPA attacks. A threshold implementation of Ascon just requires about 8Â kGE of chip area, which is only 3.1 times larger than the unprotected low-area optimized implementation.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microprocessors and Microsystems - Volume 52, July 2017, Pages 470-479
Journal: Microprocessors and Microsystems - Volume 52, July 2017, Pages 470-479
نویسندگان
Hannes Gross, Erich Wenger, Christoph Dobraunig, Christoph Ehrenhöfer,