Implementation of efficient SR-Latch PUF on FPGA and SoC devices

In this paper we present a reliable and efficient SR-Latch based PUF design, with two times improvement in area over the state of the art, thus making it very attractive for low-area designs. This PUF is able to reliably generate a cryptographic key. The PUF response is generated by quantifying the number of oscillations during the metastability state for preselected latches. The derived design has been verified on 25 Xilinx Spartan-6 FPGAs (XC6SLX16) and 10 Xilinx Zynq SoC (XC7Z010) devices. The design exhibited ∼49% uniqueness figures when tested on both types of FPGAs. The reliability figures were >94% for temperature variation (0-85 °C) and ±5% of core voltage variation.