Efficient integration of coprocessor in LEON3 processor pipeline for System-on-Chip design

In this paper, we have proposed an efficient method for integrating longer pipeline coprocessors with SPARCv8 compliant processor implementations that requires minimum changes in the existing processor pipeline. The proposed integration method is independent of the length of the coprocessor pipeline. We have used COordinate Rotation DIgital Computer (CORDIC) core as the coprocessor that has been integrated with SPARCv8 based LEON3 processor. Only a subset of the coprocessor instructions defined in the Instruction Set Architecture (ISA) are required in our proposed method. The required synchronisation of data and control signals between the coprocessor and LEON3 pipeline has been presented in detail. The performance of the resulting closely-coupled design is compared with bus-based integration in terms of speed, power and area in the System-on-Chip (SoC) design, and both FPGA and ASIC results are reported. Our proposed integration method shows significant improvements over bus-based method for applications that require consecutive coprocessor operations in terms of CPI metric along with substantial reduction in number of cycles. Similar strategy can be employed for integration with coprocessors having different pipeline lengths.