High speed FPGA-based data acquisition system

An application that involves high speed signal changes at input side makes it very important to have a high speed Data Acquisition without loss of any data. This paper discusses FPGA design architecture programed by VHDL firmware which involves high speed Analog to digital converter (ADC) with sampling rate of 80 mega samples per second, Direct Memory Access (DMA) programed in such a way which transfers data without loss of single data sample and high speed Dual Data Rate 3 (DDR3) SDRAM to store digitized data for further manipulations. It also describes data-rate, and speed achieved to transfer data and plot a graph of digital value which shows there is no loss of data.