FPGA accelerator for real-time SIFT matching with RANSAC support

- A pipelined FPGA-based architecture for real-time SIFT feature matching with RANSAC support is proposed.
- Each feature in the current video frame is matched among the features of the previous frame that are saved to a RAM-based moving window in one clock cycle, i.e. 40 ns considering Cyclone IV technology.
- RANSAC is implemented in a highly paralleled circuit and each run lasts for as many clock cycles as the number of the selected random samples.
- A resource efficient SIFT descriptor computation module is presented.

Scale-Invariant Feature Transform (SIFT) has been considered as one of the more robust techniques for the detection and matching of image features. However, SIFT is computationally demanding and it is rarely used when real time operation is required. In this paper, a complete FPGA architecture for feature matching in consecutive video frames is proposed. Procedures of SIFT detection and description are fully parallelized. At every clock cycle, the current pixel in the pipeline is tested and if it is a SIFT feature, its descriptor is extracted. Furthermore, every detected feature in the current frame is matched with one among the stored features of the previous frame, using a moving window, without violating pixel pipelining. False matches are rejected using random sample consensus (RANSAC) algorithm. Each RANSAC run lasts for as many clock cycles as the number of the selected random samples. The architecture was verified in the DE2i-150 development board. In the target hardware, maximum supported clock frequency is 25 MHz and the architecture is capable to process more than 81 fps, considering image resolution of 640 × 480 pixels.

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