کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
4956812 1444593 2017 12 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر شبکه های کامپیوتری و ارتباطات
پیش نمایش صفحه اول مقاله
Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs
چکیده انگلیسی

In this paper we investigate the effects of asymmetric organization and depths of Network-on-Chip (NoC) router buffers among dies in heterogeneous 3D-System-on-Chips (SoCs). In our novel approach the properties of the routers are aligned with the characteristics of the technological nodes per layer. We call these designs Asymmetric 3D-NoCs (A-3D-NoCs). In this work we demonstrate potentials of A-3D-NoCs in comparison to a conventional, symmetric 3D-NoC: Applying asymmetric buffer reorganization we achieve area savings of 8.3% and power savings of 5.4% for link buffers while accepting a minor average system performance loss of 2.1%. With additional asymmetry in buffer depth up to 28% cost savings and 15% power reduction are given in combination with a 4.6% performance decline. Thus, the proposed buffer organization scheme is applicable for cost and power critical applications of NoCs in heterogeneous 3D-SoCs.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microprocessors and Microsystems - Volume 48, February 2017, Pages 36-47
نویسندگان
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