کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
4956843 1364712 2016 7 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Efficient FPGA implementation of modular multiplication based on Montgomery algorithm
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر شبکه های کامپیوتری و ارتباطات
پیش نمایش صفحه اول مقاله
Efficient FPGA implementation of modular multiplication based on Montgomery algorithm
چکیده انگلیسی
In order to improve the efficiency of modular multiplication algorithm for FPGA implementation on the prime field modular, an efficient scheme is proposed to accomplish 256 × 256 bits modular multiplication algorithm. The embedded IP cores of Xilinx FPGA are efficiently utilized to design 512-bit addition and 256 × 256 bits multiplier. Moreover, the above modules are used to complete Montgomery modular multiplication algorithm. Compared with traditional implementation method, almost 50% running efficiency is improved in our scheme, which has important value to implement complicated cryptographic processor in hardware environment.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microprocessors and Microsystems - Volume 47, Part A, November 2016, Pages 209-215
نویسندگان
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