کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
4956891 | 696573 | 2016 | 12 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
A practical automated timing and physical design implementation methodology for the synchronous asynchronous interface and multi-voltage domain in high-speed synthesis
ترجمه فارسی عنوان
یک روش زمانبندی خودکار فیزیکی و روش اجرای فیزیکی برای رابط واسط ناهمزمان همزمان و دامنه چند ولتاژ در سنتز با سرعت بالا
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
شبکه های کامپیوتری و ارتباطات
چکیده انگلیسی
In a high-speed synthesis design environment, designers struggle to ensure that multi-clock and multi-power interfaces are designed, placed, connected and timed correctly. Identifying and applying proper timing constraints such as “no cycle stealing” at synchronous and asynchronous domain interfaces in macro synthesis, unit and chip timing are essential. Standard cell library characterization, for multi-power and timing challenges due to an additional delay for level translator circuitry, demand careful implementation in a high-speed synthesis methodology. We propose a pseudo algorithm and methodology for synthesis and timing that will correctly identify synchronous and asynchronous interfaces. Our proposed methodology shows how these interface paths should be excluded from “cycle stealing” and yet, take full advantage of slack borrowing for the rest of the design. We find â¼28% and â¼80% timing path improvement in two of the units for IBM's Power8TM (P8) microprocessor. As an alternative to high-effort custom design, we develop a synthesis-based physical design methodology that incorporates the use of a level translator, enabling designers to address major issues that encompass dual-voltage solutions in high-speed design. We find â¼50% physical design effort savings using this methodology. P8 is a 12-core, 649 mm2, 4.2B transistor chip fabricated in IBM's 22-nm Silicon On Insulator (SOI) technology, which is fully functional to support a wide range of high performing systems with an operating frequency greater than 4.5Â GHz.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microprocessors and Microsystems - Volume 45, Part B, September 2016, Pages 241-252
Journal: Microprocessors and Microsystems - Volume 45, Part B, September 2016, Pages 241-252
نویسندگان
Mozammel Hossain, John Badar, Jack DiLullo, Tom Chen,